1. Field of the Invention
The present general inventive concept relates to a control system including a main controller and at least one peripheral controller. More specifically, the present general inventive concept relates to a method and system to reduce a load to a system bus in a control system.
2. Description of the Related Art
General computer architecture, such as a workstation, includes a bus that interconnects function blocks, such as a central processing unit (CPU), applications, and attachments (devices). Each block functions as a master or a slave.
FIG. 1 is a construction of a conventional multifunctional peripheral (MFP). The conventional MFP includes a main controller 10 having a CPU 110, and devices 20 through 60. The main controller 10 includes the CPU 110 having a memory therein, an internal device 130, and a plurality of channels 120 through 12N. The CPU 110 is connected with the plurality of channels 120 through 12N over a system bus 150.
The devices 20 through 60 each include a controller (not shown), to respectively control their components. Hereinafter, the controllers in the devices 20 through 60 are referred to as “peripheral controllers.” The channels 120 through 12N and the devices 20 through 60 are interconnected using serial lines. As shown in FIG. 1, the control system of the conventional MFP includes the main controller 10, and the peripheral controllers of the devices 20 through 60.
The CPU 110 processes graphic data and controls overall operations of the system. The devices 20 through 60 represent peripherals in the MFP. For instance, the first device 20 may be a user interface, such as a display and an input part (keyboard), the second device 30 may be a duplex document feeder, the third device 40 may be a finisher, the fourth device 50 may be a toner cartridge, and the N-th device 60 may be a printer engine. As mentioned above, the devices 20 through 60 each include a controller.
Typically, the devices 20 through 60 function independently with respect to each other to reduce a load to the CPU 110, but do not function completely independently from the CPU 110. The devices 20 through 60 can receive or transfer required data from or to the CPU 110. The CPU 110 and the devices 20 through 60 communicate data using the system bus 150 and the serial lines.
The following explanation is directed to the system bus 150 and the serial lines used to transfer data between the CPU 110 and the devices 20 through 60. In FIG. 1, the system bus 150 guarantees a high data transfer rate, and the serial lines guarantee a relatively low data transfer rate as compared with the system bus 150.
The first device 20 is connected to the CPU 110 over the first channel 120, and the second device 30 is connected to the CPU 110 over the second channel 121. The third device 40 is connected to the CPU 110 over the third channel 122, and the fourth device 50 is connected to the CPU 110 over the fourth channel 123. The N-th device 60 is connected to the CPU 110 over the N-th channel 12N.
Data transmitted to the CPU 110 can be categorized according to data volume, into control data having small data volume and graphic data having large data volume. Generally, the devices 20 through 60 transmit the control data having small data volume, and a scanner 70 transfers graphic data having large data volume to the CPU 110.
The devices 20 through 60 are connected to the channels 120 through 12N using the serial lines providing a low data transfer rate, and the scanner 70 is connected with a bridge 140 using a parallel bus 80 providing a high data transfer rate. The scanner 70 is connected this way because the scanner 70 requires a bus that can guarantee a high data transfer rate so as to transfer scanned data to the CPU 110. The bridge 140 is provided for input and output processes with a direct memory access (DMA) controller, which is assigned with certain functions of the main controller 10.
FIGS. 2A and 2B illustrate conventional structures of the channels 120 through 12N of FIG. 1.
FIG. 2A depicts a universal asynchronous receiver/transmitter (UART). The UART is provided to the channels 120 through 12N and the devices 20 through 60. Referring to FIG. 2A, the UART interfaces data, chip select (CS), read and write (R/W), and clock (CLK) signals. That is, the CS signals instruct the UART to turn on or off the channels 120 through 12N. The R/W signals instruct the UART to transfer data to the channels 120 through 12N or to read data from the channels 120 through 12N. The UART synchronizes the channels 120 through 12N using the received CLK signals. The channels 120 through 12N are connected to the respective devices 20 through 60 using the serial lines.
FIG. 2B depicts a register that transmits and receives three control data signals. Unlike the control data transmitted and received using the single serial line in FIG. 2A, the control data in FIG. 2B are transmitted and received using respective dedicated lines.
Referring back to FIG. 1, as the conventional MFP utilizes the plurality of channels 120 through 12N, overload is caused to the system bus 150 interconnecting the CPU 110 and the channels 120 through 12N. In this situation, it is hard to efficiently transfer the graphic data to the CPU 110 via the bridge 140. Furthermore, as the number of the devices increases, the number of channels also increases. The increased number of the devices also increase a load to the system bus 150. Thus, a method is required to increase the number of devices without changing the control system and without increasing a load of a system bus.